FIG. 1 and FIG. 2 show partial schematic diagrams of an array substrate. As shown in the diagrams, the array substrate comprises a thin film transistor; the thin film transistor includes an active layer 40, a channel region 41 formed in the active layer 40, an ohmic contact layer 51 and an ohmic contact layer 52 disposed on the active layer 40, a drain electrode 20 disposed on the ohmic contact layer 51 and a source electrode 30 disposed on the ohmic contact layer 52; and the drain electrode 20 is electrically connected with a pixel electrode 10.